Chat with us, powered by LiveChat computer architecture (TOPIC Synchronous DRAM) | paledu.org
  

you are required to do a term research paper (or a project) and presentation, each presentation is about 10 minutes long. Your task is to search and select a relatively new research topic or project (list of suggested topics below), you can also search and select recent research related to computer Architecture from one of the conferences and journals. 

Deliverables: 

  1. Review research paper of the main topic selected with at least
  2. 3 relevant research papers as references. Use APA style, Minimum is 5 pages including the cover page and the reference page. (SafeAssign Enabled). If you select a project then the source code along with the documentation will be required. You can select either a review research paper or a Project but not both: Due Week 14
  3. Summary presentation using PPT or Prezzi or any other presentation software: Due Week 14

4. Online Presentation, 10 min per group, if you can’t make an online live presentation, you can record a video and submit it: Due Week 14

See discussions, stats, and author profiles for this publication at: https://www.researchgate.net/publication/237783032

The New D RAM Interfaces: SDRAM, D RDRAM a nd Variants

Conference Paper · October 2000

DOI: 10.1007/3-540-39999-2_3 · Source: CiteSeer

CITATIONS

6
READS

152

3 authors:

Some of the authors of this publication are also working on these related projects:

Low Power Architecture View project

University of Michigan, Ann Arbor View project

Brian T. Davis

Embry-Riddle Aeronautical University

17 PUBLICATIONS   629 CITATIONS   

SEE PROFILE

Bruce Jacob

University of Maryland Global Campus

166 PUBLICATIONS   4,822 CITATIONS   

SEE PROFILE

Trevor N. Mudge

University of Michigan

422 PUBLICATIONS   22,686 CITATIONS   

SEE PROFILE

All content following this page was uploaded by Trevor N. Mudge on 08 February 2014.

The user has requested enhancement of the downloaded file.

1

Synchronous DRAM Architectures, Organizations,
and Alternative Technologies

Prof. Bruce L. Jacob

Electrical & Computer Engineering Dept.
University of Maryland

College Park, MD 20742
http://www.ece.umd.edu/~blj/

December 10, 2002

1 DRAM TECHNOLOGY OVERVIEW

This section describes the structural organization of dynamic ran-
dom-access memories (DRAMs), their operation, and the evolution
of their design over time.

1.1 Basic Organization and Operation of a Conventional
DRAM

DRAM is the “computer memory” that you order through the mail
or purchase at Best Buy or CompUSA. It is what you put more of
into your computer as an upgrade to improve the computer’s perfor-
mance. DRAM appears in personal computers (PCs) in the form
shown in Figure 1—the figure shows a

memory module

, which is a
small computer board (“printed circuit board”) with a handful of
chips attached to it. The eight black rectangles on the pictured mod-
ule contain

DRAM chips

. Each DRAM chip contains one or more

memory

arrays

, rectangular grids of storage cells with each cell
holding one bit of data. Because the arrays are rectangular grids, it is
useful to think of them in terms associated with typical grid-like
structures—a good example of which is a Manhattan-like street lay-
out with avenues running north-south and streets running east-west.
When one wants to specify a rendezvous location in such a city, one
simply designates the intersection of a street and an avenue, and the
location is specified without ambiguity. Memory arrays are orga-
nized just like this, except whereas Manhattan is organized into

streets

and

avenues

, memory arrays are organized into

rows

and

col-
umns

. A DRAM chip’s memory array with the rows and columns
indicated is pictured in Figure 2. By identifying the intersection of a
row and a column, a computer’s central processing unit (CPU) can

access an individual storage cell inside a DRAM chip so as to read
or write the data held there. This is accomplished by sending both a

row address

and a

column address

to the DRAM.
One way to characterize DRAMs is by the number of memory

arrays inside them. Memory arrays within a memory chip can work
in several different ways: they can act in unison, they can act com-
pletely independently, or they can act in a manner that is somewhere
in between the other two. If the memory arrays are designed to act in
unison, they operate as a unit, and the memory chip ty

See discussions, stats, and author profiles for this publication at: https://www.researchgate.net/publication/269711137

Design and Implementation of SDRAM Controller in FPGAs

Article · July 2014

CITATIONS

0
READS

2,784

1 author:

Sahul Hameed

Indian Space Research Organization

4 PUBLICATIONS   0 CITATIONS   

SEE PROFILE

All content following this page was uploaded by Sahul Hameed on 19 June 2015.

The user has requested enhancement of the downloaded file.

See discussions, stats, and author profiles for this publication at: https://www.researchgate.net/publication/269711137

Design and Implementation of SDRAM Controller in FPGAs

Article · July 2014

CITATIONS

0
READS

2,784

1 author:

Sahul Hameed

Indian Space Research Organization

4 PUBLICATIONS   0 CITATIONS   

SEE PROFILE

All content following this page was uploaded by Sahul Hameed on 19 June 2015.

The user has requested enhancement of the downloaded file.

<a href=”https://www.researchgate.net/profile/Sahul-Hameed?enrich